Stack Processor, Pt. 2 (cont.)

I guess it would be doable to just have a 3-byte instruction that loads a data word from a literal address to the stack? Basically it would be a slightly optimized form that doesn’t first put the address onto the stack itself:
1. Decode first byte of instruction, push TOS
2. Move first address byte into the high byte of the SRAM address latch
3. Move the second byte into the low byte of the SRAM address latch
4. Latch the SRAM data bus into the TOS register

Would it make sense to have some sort of paging for literal SRAM access? Basically, have the high N bits of the address be adjustable through a separate register and then have the remaining bits encoded in the instruction.

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